1. Field of the Invention
The present invention relates to an operation error verification method of a writing apparatus and a creation apparatus of operation error verification data for the writing apparatus, and for example, relates to an operation error verification method or a creation apparatus of verification data of an electron beam writing apparatus.
2. Related Art
A Lithography technique which takes a part of the development of miniaturization of semiconductor devices is only a process, in which a pattern is generated, in semiconductor manufacturing processes and is very important. In recent years, with the advancement in integration density of an LSI, circuit line widths required for semiconductor devices are miniaturized year by year. In order to form desired circuit patterns on the semiconductor devices, precise original patterns (to be also referred to as a reticle or a mask) are required. In this case, an electron beam writing technique has an essentially excellent resolution, and is used in production of precise original patterns.
FIG. 28 is a conceptual diagram for explaining an operation of a variable-shaped electron beam (EB) writing apparatus. The variable-shaped electron beam writing apparatus operates as follows. An oblong, for example, rectangular opening 411 to shape an electron beam 442 is formed in a first aperture plate 410. A variable-shaped opening 421 to shape the electron beam 442 having passed through the opening 411 of the first aperture plate 410 into a desired oblong shape is formed in a second aperture plate 420. The electron beam 442 irradiated from a charged particle source 430 and having passed through the opening 411 of the first aperture plate 410 is deflected by a deflector, passes through a part of the variable-shaped opening 421 of the second aperture plate 420, and is irradiated on a target object placed on a stage continuously moving in one predetermined direction (for example, an X direction). More specifically, an oblong shape which can pass through both the opening 411 of the first aperture plate 410 and the variable-shaped opening 421 of the second aperture plate 420 is written in a write region of a target object 440 placed on the stage continuously moving in the X direction. A scheme which causes an electron beam to pass through both the opening 411 of the first aperture plate 410 and the variable-shaped opening 421 of the second aperture plate 420 to form an arbitrary shape is called a variable-shaping scheme.
Upon such electron beam writing, firstly, a layout of a semiconductor integrated circuit is designed and layout data is generated. Then, data of chips satisfying certain conditions contained in the layout data are merged and the layout data is reconstructed. Then, the chip-merged layout data is converted to generate write data used by an electron beam writing apparatus. Further, a figure is divided into shot sizes for actual shots of the electron beam based on the write data, and then writing is performed.
Here, a write error may occur in a process between input of the layout data into the writing apparatus and inspection of the target object on which a figure pattern is formed. If a write error occurs after a writing apparatus starts to form a pattern, the simplest method of reproducing the error for examination is to use completely the same data. However, if the processing time from starting to form a pattern to reach to a portion that has caused the error is long, it takes a very long time to examine the error, unfortunately. Thus, the inventors have proposed to extract a part of layout data necessary for operation of the function causing a write error from the layout data, perform merge processing based on the part of the extracted layout data, and create verification data to verify the write error from the layout data after the merge processing (for example, see Published Unexamined Japanese Patent Application No, 2008-047722 (JP 2008-047722A). By performing a reproduction test using verification data created by automatically extracting a pattern at the portion of error occurrence in this manner, it becomes possible to reduce the examination time of errors.
However, if the same chip is arranged at a plurality of portions in a layout, a problem may arise with the technique according to the JP 2008-047722A alone. This is because generally only one piece of chip data is used as a basis and pieces of pattern data created by referring to the same chip data as a basis are arranged at respective portions. Thus, if verification data is created by automatically extracting pattern data at a portion of error occurrence, pieces of the pattern data regarding the portion corresponding to the portion of error occurrence are similarly arranged for chips arranged in other regions. Therefore, when a reproduction test is performed, the same test is also performed for portions other than the portion corresponding to error occurrence, posing a problem that loss of the verification time is caused.
In a layout in which the same chips are arranged at a plurality of portions, as described above, there is a problem that pieces of verification data are also created for portions other than a portion that has originally caused an error. Particularly for a layout in which the number of chip arrangements is large, verification is performed also for regions that originally need not be verified to waste verification time, and thus, it may take longer than the verification time that would have been originally needed, unfortunately.